| 摘要 |
<p>PURPOSE:To facilitate simulation and testing by forming a timing signal operating an internal memory based on a control signal outputted from a micro processor and an operation clock. CONSTITUTION:Timing control circuits 8 provided in internal ROM 2 and internal RAM 3 generate the timing signal operating a decoder and a sense amplifier based on the control signals such as a selection signal, a read signal and a write signal, all of which are outputted from CPU 1, and reference clock signals CK1 and CK2 supplied from a clock generation circuit 7 to CPU 1. Since all the timing signals operating the internal memory are synchronized with the operation clock of CPU 1, the operation timing of internal ROM 2 and RAM 3 is decided so as to facilitate simulation and testing, and the evaluation of an operation margin is facilitated.</p> |
