发明名称 LARGE SCALE INTEGRATED CIRCUIT
摘要 <p>PURPOSE:To improve efficiency for the test of a memory address generating part and the test of program debugging by respectively connecting the outputs of the plural memory address generating parts to external terminals by buses. CONSTITUTION:The outputs of memory address generating parts 1-3, which apply addresses to a memory 10, are connected by external terminals 31-33 by buses 21-23 so as to be monitored in the external terminals 31-33. Thus, for testing the outputs of the memory address generating parts 1-3, it can be decided by monitoring the outputs in the external terminals 31-33 whether they are correct or not. When bugging is investigated, it can be easily discovered and the efficiency for the test is improved.</p>
申请公布号 JPH0344781(A) 申请公布日期 1991.02.26
申请号 JP19890181004 申请日期 1989.07.12
申请人 FUJITSU LTD 发明人 KAWAMURA SEIJI;NAGASAWA TATSUYA;ONISHI KUMIKO;WATANABE TOMOHARU
分类号 G06F11/30;G06F15/78 主分类号 G06F11/30
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