发明名称 PHASE SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To enable a circuit to follow up the frequency of an input signl by calculating the mean period of the input signal by counting a clock signal, and then dividing the frequency of the clock singal according to the mean period. CONSTITUTION:When an input signal is inputted to a terminal, a phase information extractor 2 outputs differential pulses corresponding to the prescribed phase of the input signal. A counter 3 counts the differential pulses and sends out an output pulse at every N periods of the input signal, thereby resetting counters 4 and 5, and a memory 6. A counter 4, on the other hand, sends out an output pulse every time an N-number of output clock pulses from an oscillator 8 are counted, and this output pulse is counted by a counter 5 to store the memory 6 with the number of clock pulses which corresponds to the mean period of the input signal. A counter 7 divides the frequency of the clock pulses by the value stored in the memory 6 and outputs the result. A phase comparator 9 and an up- down counter 10 perform phase comparison between the input signal and output signal to send a phase correction signal to the counter 7.
申请公布号 JPS57173230(A) 申请公布日期 1982.10.25
申请号 JP19810056949 申请日期 1981.04.17
申请人 HITACHI SEISAKUSHO KK 发明人 ASHIDA AKIRA
分类号 H03L7/06;H03L7/099;H04L7/00;H04L7/02;H04L7/027;H04L7/033 主分类号 H03L7/06
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