| 摘要 |
PURPOSE:To reduce the circuit scale and to increase the processing speed by placing a divider before an adder and forecasting it from input digital signals that rounding of the result obtained by dividing the addition result of input digital signals by the divider will bring about carry and performing rounding. CONSTITUTION:Input digital signals 1 and 2 are divided in dividers 3 by 4, and results have lower two bits rounded down and are added by an adder 4. In this case, dividers 3 are placed before the adder 4, and it is forecasted by input digital signals that rounding of the result obtained by dividing the addition result of input digital signals 1 and 2 by the divider 3 will bring about carry, and rounding is performed. Thus, the word length of the adder 4 is shortened, and a device having a smaller circuit scale and a high processing speed is obtained. |
