| 摘要 |
PURPOSE:To prevent a demodulated data from having a jitter component while keeping high response using a DPLL circuit by using the DPLL circuit and changing the frequency of a 1st clock signal based on the tendency of production of an up/down command signal. CONSTITUTION:The period of a 2nd clock signal CK 2 is changed by forming a digital phase locked loop(DPLL) to output a demodulation data immediately following a change in an input data DIN. Then the tendency of a change in the time base of the input data DIN is detected based on an UP command signal and the DOWN command signal of the DPLL circuit to form a clock frequency control signal, which is given to a clock generator 11, thereby varying the frequency of the 1st clock signal CK 1. Thus, the data is demodulated with excellent response and without causing a jitter component. |
