发明名称 |
ECL/CML pseudo-rail circuits, cutoff driver circuit, and latch circuit. |
摘要 |
<p>A pseudo-rail circuit is coupled between the differential output gate or buffer of an emitter coupled logic or current mode logic (ECL/CML) circuit and the high potential level power rail. The pseudo-rail circuit provides a pseudo-rail node (A). A first clamp circuit is coupled to the pseudo-rail node for clamping the pseudo-rail node at a first potential level (GND) in response to a first control signal. A second clamp circuit is coupled to the pseudo-rail node for clamping at a second potential level in response to a second control signal. A clamp switching circuit alternately applies the first and second clamp circuits to the pseudo-rail node in response to the control signals. As a cutoff driver circuit, the first clamp circuit of the pseudo-rail circuit applies the high potential level of the power rail to the pseudo-rail node. The second clamp circuit pulls down the pseudo-rail node to hold the output of the differential output gate in the cutoff state. An output enable (OE) differential gate or buffer provides the clamp switching circuit. The pseudo-rail circuit is incorporated directly in a latch circuit to initiate the cutoff state in response to an OE cutoff signal without losing latched data and without requiring an additional output buffer stage.</p> |
申请公布号 |
EP0407869(A2) |
申请公布日期 |
1991.01.16 |
申请号 |
EP19900112727 |
申请日期 |
1990.07.04 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
ESTRADA, JULIO R. |
分类号 |
H03K3/286;H03K3/2885;H03K19/00;H03K19/086 |
主分类号 |
H03K3/286 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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