Integrated circuit arrangement

摘要

In the arrangement of an integrated circuit chip 11 on a multilayered circuit carrier (substrate 15) substrate bond connections 20 are arranged in a narrow connection strip 26 outside the circus boundary 13 in accordance with the geometry of the chip connections 12. The front ends of vias 16 which are of large area in cross-section compared with the conductor-path transverse dimensions are situated on a wider edge strip 25 beneath the chip mounting region 22 and are connected by thin conductor paths 19 to the substrate bond connections 20.