发明名称 |
Binary adder circuit with improved inputs |
摘要 |
A binary calculation circuit has a logic operator acting as an exclusive-OR gate generating a first intermediate signal which is an exclusive-OR of a first input and a carry-in input. An inverter generates a second intermediate signal. A second logic operator generates a first output bit which is a symmetrical exclusive-OR of a second input and both the first and second intermediate signals. A second output bit is a symmetrical trigger function of the first and second input, depending on the first and second intermediate signals, and is generated in a transmission gate. Since the carry-in signal passed via the first and second intermediate signals is applied directly to transistors of the transmission gate, carry propagation delay is reduced.
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申请公布号 |
US4985862(A) |
申请公布日期 |
1991.01.15 |
申请号 |
US19880248089 |
申请日期 |
1988.09.23 |
申请人 |
ETAT FRANCAIS REPRESENTE PAR LE MINISTRE DELEGUE DES POSTES ET TELECOMMUNICATIONS (CENTRE NATIONAL D'ETUDES DES TELECOMMUNICATIONS) |
发明人 |
HMIDA, HEDI;DUHAMEL, PIERRE |
分类号 |
G06F7/38;G06F7/50;G06F7/501;G06F7/503;G06F7/506;G06F7/508;G06F7/52;G06F7/525;G06F7/527;G06F7/53 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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