| 摘要 |
<p>For on-chip self testing, a first data register (10) performs storage or transfer of data, operates in a scan mode or generates pseudo-random numbers (PRN), and a second data register (60) performs storage or transfer of data, operates in a scan mode or performs signature analysis. Data initialisation of the registers occurs automatically when operating in a test mode. Each stage (50,...,100,...) of each register includes a mode controller (33,83) which in the data mode passes data from a data input transmission gate (22,72) to a storage flip flop (38,90), or initialisation data from an initialisation transmission gate (20,70) at the beginning of a test mode. Also during the test mode, data output from each stage is fed back through exclusive-OR gates (40,42,90,92) and a transmission gate (32,82) to a first one of the stages (Stage A). Data and test mode are selected by a test enable signal applied through conditioning logic (12,14,16,18,24,26; 62,64,66,68,74,76) to each stage.</p> |
