发明名称 RECEPTION TIMING CIRCUIT
摘要 PURPOSE:To simultaneously satisfy all connection constitutions of interface supported by a network terminating device by providing an FL change point detecting circuit, a frequency dividing circuit, a delay circuit, a frame synchronizing circuit, and a separating circuit. CONSTITUTION:A change point detecting circuit 14 which detects the change point from a frame bit part F to a DC balance bit part L of the frame synchronizing signal of a reception frame, a frequency dividing circuit 16 initialized by the detected change point, a delay circuit 18 which delays the output clock of the frequency dividing circuit, a frame synchronizing circuit 21 which detects the reception signal by the output clock of the delay circuit and decides the violation rule prescribed by CCITTI. 430 to acquire frame synchronism, and a separating circuit 12 which separates a signal channel from the reception signal by the output clock of the delay circuit are provided. Thus, the reception clock circuit is obtained which simultaneously satisfies all constitutions of short- distance passive bus connection, 1:1 connection, and extended passive bus connection.
申请公布号 JPH02312330(A) 申请公布日期 1990.12.27
申请号 JP19890133849 申请日期 1989.05.26
申请人 NEC CORP 发明人 ONO TATSUHIRO
分类号 H04J3/06;H04J3/00;H04L7/08;H04L25/49 主分类号 H04J3/06
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