| 摘要 |
An improved memory utilization arrangement for a VITERBI decoder which allows the amount of memory required for storing state metrics to be minimized. Both old and new state metrics are required to be stored. This scheme utilizes memory locations for which old metrics have been previously read for storing the newly calculated metrics. In one implementation of this invention, a barrel shifter is used to calculate the address at which to store and retrieve the appropriate metrics. Another implementation employs a shift register with a shifting and inserting operation to align the metrics in the proper order and at the same time store the new metrics for subsequent calculations. As a result of the saving of memory, the amount of memory and power consumption are reduced substantially.
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