| 摘要 |
PURPOSE:To form a high density gate wiring without restriction of pattern resolution capability of a projection aligner, by forming a pattern turing to the center of a pair of gate electrodes, on the side wall part of a circuit pattern formed by projection alignment, and forming a desired gate wiring on the side wall part of the pattern. CONSTITUTION:After an insulating layer 15 is formed on the surface of first patterns 12, 13 formed on the surface of a semiconductor substrate 20, said insulating layer 15 is etched back, and the insulating layer 15 left only on the approximate near side surface of the first patterns 12, 13 is formed as a second pattern 15. After the first patterns 12, 13 are eliminated and conducting layers 17, 18 are formed on the surfaces of the second pattern 15 and the semiconductor substrate 20, said conducting layers 17, 18 are etched back; only the conducting layers 17, 18 on the vicinity side part of the second pattern 15 are left; the second pattern 15 is eliminated, thereby forming a gate wiring 21 of the conducting layers 17, 18. As a result, a high density gate wiring 21 having two times density of the first patterns 12, 13 can be formed. Thereby a high density gate wiring can be formed without restriction of pattern resolution capability of a projection aligner. |
