| 摘要 |
A semiconductor integrated circuit chip is provided comprising a substrate 1, a dielectric layer 3, deposited on the substrate 1 and one or more conductive tracks 4, 5 formed on the dielectric layer 3, at least part of the dielectric layer 3 which is along at least one edge of the conductive tracks 4, 5 and which is adjacent to the part of the dielectric layer 3 which underlies the conductive track 4, 5 being etched away to form an air gap 16 in the region where fringing fields and/or lateral fields exist, thereby to reduce the stray interconnection capacitance between the conductive tracks 4,5 and the substrate 1 (Figure 2). <IMAGE> |
