发明名称 PLL CIRCUIT
摘要 PURPOSE:To attain the acceleration of operating speed and a low cost due to the simplification of circuit constitution by providing plural phase locked loops by using variable frequency oscillators with the same characteristic, and using the output signal of a loop filter generated by the phase locked loop on one side in control for the phase locked loop on the other side. CONSTITUTION:A second phase comparator 22 inputs a reference signal Vr and a feedback signal FB2, and detects the phase difference of both signals, and outputs a phase difference signal to the loop filter 23. The loop filter 23 eliminates a high frequency component in the phase difference signal, and outputs a low frequency signal to a second variable frequency oscillator 25. The variable frequency oscillator 25 is controlled by the output of the loop filter 23, and makes its oscillation frequency coincide with the frequency of the reference signal. A signal addition circuit 14 adds the output of the first and second loop filters 13 and 23, and controls a first variable frequency oscillator 15 by inputting an added signal. Thereby, it is possible to attain the acceleration of the operating speed and the low cost.
申请公布号 JPH02244820(A) 申请公布日期 1990.09.28
申请号 JP19890064197 申请日期 1989.03.16
申请人 OKI ELECTRIC IND CO LTD 发明人 OOYA TAKASHI
分类号 H03L7/087;H03L7/07;H03L7/10 主分类号 H03L7/087
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