发明名称 DEETAPARUSUJUSHINKAIRO
摘要 PURPOSE:To prevent malfunction due to virtual pulses, by receiving only normal data pulses, through the constitution of a reception circuit so that the range of receptionable pulses can be limited with the pulse width and voltge. CONSTITUTION:A reception circuit consisting of comparators A1-A4, resistors R1-R13, capacitors C1-C4 and diodes D1-D3 is connected to data transmission lines L1, L2 in common use for power supply. Further, the comparator A1 of the reception circuit is provided with a time constant circuit consisting of resistors R4, R5 and a capacitor C2, and the receptionable pulse width is limited by comparing a reference voltage of the comparator A2 with a voltage of the capacitor C2. The peak value of the pulse voltage is limited with the comparators A3 and A4 including the time constant circuit consiting of the capacitor C3 and the diode D3, only normal data pulses are received, the data pulse is outputted to an output terminal T to prevent malfunction due to virtual pulses.
申请公布号 JPH0239904(B2) 申请公布日期 1990.09.07
申请号 JP19810160723 申请日期 1981.10.08
申请人 MEISEI DENKI KK;NIPPON DENSHIN DENWA KK 发明人 HASHIMOTO KOSUKE;IWANAMI MICHIAKI;KUDO MASARU
分类号 H03M5/12;H03K5/1252;H04L1/20;H04L25/03;H04L25/08;H04Q3/58 主分类号 H03M5/12
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