发明名称 |
Adaptive input logic for phase adjustments |
摘要 |
Systems and methods are disclosed to provide static and/or dynamic phase adjustments to a data signal relative to a clock signal. For example, the data signal may be delayed by a coarse delay and/or a fine delay to match the timing of the clock signal independently for each input path (e.g., per input pad). The delay may be as a function of positive and/or negative clock edges.
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申请公布号 |
US7034596(B2) |
申请公布日期 |
2006.04.25 |
申请号 |
US20030365083 |
申请日期 |
2003.02.11 |
申请人 |
LATTICE SEMICONDUCTOR CORPORATION |
发明人 |
ANDREWS WILLIAM B.;SCHOLZ HAROLD;BRITTON BARRY K. |
分类号 |
H03K3/00;H03H11/26;H03K5/00;H03K5/13;H03L7/081;H04B;H04L7/033 |
主分类号 |
H03K3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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