| 摘要 |
<p>PURPOSE:To constitute a flip-flop whose setup time is zero without retarding a data output by latching a data with a proper time delay from the edge of an external control signal, and switching a data from an external circuit and a latch output. CONSTITUTION:The title circuit consists of a circuit 1 generating a pulse with a proper time width from a clock edge, circuits C1-C4 latching an input data and output circuits C5, C6 switching the input data and the output from the latch circuits C1-C4 and the output is switched depending on a period of the pulse generated at the clock leading. Thus, the output is at first switched into the input by the clock rising to compensate the setup time, then the output is switched the latched data to output high speed data while compensating the setup time.</p> |
