| 摘要 |
PURPOSE:To integrate a circuit to detect the 0/1 alternating pattern of a multiplex signal with a circuit to establish a synchronizing state by saving a period for the synchronization of the 0/1 alternating pattern and the multiplex signal in a storage part and detecting the 0/1 alternating pattern based on the multiplex signal and a present multiplex signal. CONSTITUTION:When the preceding state of step-out information is step-out state, and a multiplex signal (d) and a 0/1 alternating signal f3 are inputted to a ROM 4, the ROM 4 releases the step-out state and outputs '0' as synchronizing address information j2. Afterwards, the ROM 4 adds synchronizing address information every one frame, never monitors 0/1 alternation until the input of the ROM 4 as the preceding state of the synchronizing address information comes to 7, and starts the monitoring of the 0/1 alternation at a point where the input comes to 7. A RAM to save the detection of the 0/1 alternating pattern in the same cycle as that of a 0/1 alternating cycle in this manner is provided. Thus, the circuit to detect the 0/1 alternating pattern can be integrated with the synchronizing circuit, and the circuit can be composed of small hardware by monitoring the new multiplex signal and the multiplex signal before the 0/1 alternation synchronization by the ROM. |
