| 摘要 |
PURPOSE:To increase the freedom of memory cell layout by arranging the gate electrode of an MISFET for load on the upper part of the gate electrode of an MISFET for driving, and arranging source drain and channel regions of the MISFET for load on the upper part of the gate electrode of the MISFET for load. CONSTITUTION:In the memory cell of a CMOS type SRAM MISFET's Qp1, Qp2 for load are arranged on the upper part of MISFET's Qd1, QD2 for driving. The MOSFET's for load have gate electrodes 34 different from gate electrodes 27 of the MISFET's for driving. As a result, source.drain and channel regions 37A-37C of the MISFET's Qp1, Qp2 for load can be laid out almost without restrictions to the gate electrodes 27 of the MISFET's Qd1, Qd2 for driving. Thereby the freedom of memory cell layout can be increased. |
