| 摘要 |
In a logic system comprising an input conditioning circuit (05), combinational logic (07), and a power amplifier solid- state output relay (09), signal paths through the logic are verified by injecting (11) a test pulse into an input filter (03, 04) and checking for its arrival at the output with an indicator (15). The test pulse duration is shorter than the response time of a solenoid load (10). The test process may be computer-controlled. <IMAGE> |
