| 摘要 |
<p>A filter processor (79) implements the LMS algorithm in an N tap digital filter (40) in (N+1) time cycles, where N is an integer. A filter structure is shown which is implemented with a processor having an update portion (81) and a convolution portion (82). A single memory (99) is shared between the two portions, and the same data is concurrently coupled to both portions for concurrent use. The filter (40) may be efficiently pipelined wherein successive adaptive and convolution operations are executed to efficiently implement an N tap filter with a minimum amount of circuitry.</p> |
