| 摘要 |
PURPOSE:To reduce input-output buffer circuits in parasitic capacitance by a method wherein a power bus is provided to an outermost periphery and input- output buffer circuit regions are arranged between an inner cell and the power bus, and external cell regions composed of the same unit cells as those of the inner cell are arranged under the power bus. CONSTITUTION:Input-output buffer circuit regions 2 are arranged at the periphery of an inner cell region 1 provided with a base cell arranged at its center, outer cell regions 4 composed of the same unit cell as those of the inner cell region 1 are provided to the outside of the input-output buffer circuit regions 2, and a power bus 3 is provided to the periphery of the input-output buffer circuit regions 2 overlapping the outer cell regions 4. And, as a bonding pad 5 connecting this semiconductor chip with a package is provided inside the input-output buffer region 2, a bonding wire is connected to the package bestriding the power bus 3. The input-output buffer regions 2 are arranged as mentioned above, so that a parasitic capacitance is present only between the chip and a semiconductor substrate and consequently an input-output buffer circuit can be reduced in parasitic capacitance. |
