| 摘要 |
PURPOSE:To reduce the scale of a circuit by reading both RAMs for bank and collating an error inspection code generated with the error inspection code read from the same address of a RAM for error inspection code storage. CONSTITUTION:Even when a 16 bit CPU 101 makes an A08 low in order to lead a low-orber 8 bit bank and makes the inverse of a UBE 9 low in order to lead a high-order 8 bit bank, control signals 12-17 of respective RAMs 102-104 are equally changed. Thus, data are always read from the RAML102 and the RAMH103 and the read data are inputted to a CODEG 109. Then, a code 18 for error inspection is generated. Simultaneously a code for inspection check, which is written when the data are written from the RAM(RAMP)104 for inspection check code storage, is read and the both codes for inspection check are compared. After that, the compared data are latched by the rise of the inverse of MRD10 and an error check is executed. |
