| 摘要 |
<p>In an information processing device for use in indicating an operation number of floating point operation elements, such as either vector elements of each vector instruction or scalar instructions, the floating point operation elements are successively counted by an adder (31) and a register (32) to produce operation number signals representative of results of the counting. The operation number signals are periodically read out of the register (32) as preceding and following operation number signals at preceding and following ones of periodical signals sent as a time signal from a digital timer, respectively, and are held in registers (36, 37). A substracter (41) substracts the preceding operation number from the following operation number to calculate a difference signal between the preceding and the following operation numbers and to provide the operation number per unit time. The difference signal is visually displayed on a display unit (42) in real time. Alternatively, each of the preceding and the following operation number signals may be memorized in a scalar register (48) together with the time signal.</p> |
