Digital phase locked loop.

摘要

A digital phase locked loop circuit produces a reference waveform synchronized with a sequence of read data signals by dividing the reference waveform which consists of 0's and 1's windows, into early and late regions for determining the occurrence of a read data pulse within a window. The occurence of a data pulse during an early or a late region produces a corresponding phase error signal. The phase error signal controls the frequency of the reference signal by increasing or decreasing the periods of the early or late regions to synchronize the reference signal with the sequence of read data signals. A period table is addressed by a combination of reference signal timing and a frequency register whose output is modulated over several cycles.