| 摘要 |
PURPOSE:To increase the quantity of transfer per unit time by distributing each of a binary element of the 1st stage of the 1st and 2nd shift registers alternately, latching the result in matching with a transmission period of a sent data and shifting the data at a period twice the transmission period by each register. CONSTITUTION:Parallel data D0 - D3 sent sequentially at a prescribed period are inputted to input terminals 10 - 13 of a data transfer system, and the 1st shift registers SR10 - SR13 comprising cascade connection of plural binary elements FF14a1, 14a2, 14a3... and FF14b1, 14b2, 14b3... and the 2nd shift registers SR20 - 23 are connected. Then a transfer clock signal CK at which a data is sent is inputted to an input terminal 15 and the signal is inputted to the 1st stage FF of the registers SR10 - 13 and each FF of the 2nd and succeeding stages of the registers SR20 - 23. Furthermore, the inverse of CK being the inversion of the clock CK by an inverter 16 is inputted to each FF of the 1st stage of the registers SR20 - 23 and each FF of the 2nd and succeeding stages of the registers SR10 - 13 and each register shifts the data at a period being twice the transmission period. |
