发明名称 HIGH-SPEED FOURIER TRANSFORM OPERATING DEVICE
摘要 <p>PURPOSE:To stabilize the operation of the device, by providing a buffer between a pipeline multiplier and a pipeline adder and storing the multiplication result in the buffer temporarily and executing the addition after the disturbance disappears in the pipeline processing of the adder. CONSTITUTION:A buffer due to a 2-port register 2 is provided between a multistage pipeline multiplier 1 and a multistage pipeline adder 5 to constitute a butterfly operator 100. A selector 3 is provided between the output of the register 2 and the adder 5, and a register 4 is connected between the output of the adder 5 and the selector 3. This operator 100 is used in a high-speed Fourier transform operating device, and one data is written in one machine cycle by the register 2, and the selector 3 and etc. are used to read two data simultaneously. The output from the multiplier 1 is written in the register 2 temporarily, and the output of the register 2 is inputted to the adder 5 simultaneously, thus stabilizing the operation of the operating device.</p>
申请公布号 JPS5878255(A) 申请公布日期 1983.05.11
申请号 JP19810175692 申请日期 1981.11.04
申请人 HITACHI SEISAKUSHO KK 发明人 ABE SHIGEO;BANDOU TADAAKI;HIRASAWA KOUTAROU;IDE TOSHIYUKI
分类号 G06F17/14;(IPC1-7):06F15/332 主分类号 G06F17/14
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