| 摘要 |
<p>PURPOSE:To facilitate to control data from a data transmitter by reading block data at a processing speed in a device in parallel to the fact that the block data are alternately written at the high order and low order address memory areas of a memory. CONSTITUTION:At a data transmitter, each time a block data transmitting period is updated, in parallel to the fact that the block data from the data transmitter are alternately written into the low order and high order address memory areas of the memory at a processing speed in the device, the block data to the transmission line alternately are read at the data transmitting speed on the transmission line from the high order and low order address memory areas. At a data receiver, each time the block data transmitting period is updated, in parallel to the fact that the block data from the transmission line are alternately written at the data transmitting speed on the transmission line to the high order and low order address memory areas of the memory, the block data to the data receiver are alternately read out of the low order and high order memory address areas. Thus, the writing and reading control of data can be simplified.</p> |
