发明名称 |
LOGICAL SIMULATION SYSTEM |
摘要 |
PURPOSE:To reduce the number of times of the designating operation of a processor for hardware and to accelerate the setting of data at the time of restarting execution by sorting the data to be set at every processor, and setting sorted data at every processor comprehensively. CONSTITUTION:When necessity to switch a simulator is generated, a data acquiring means 4 fetches simulation state data required for the switching from the simulator 1. Fetched data is delivered to a data sorting means 5. The data sorting means 5 sorts delivered data at every processor on which the data is set. Sorted data is delivered to a data comprehensive setting means 6 at every processor. A data comprehensive setting means 6 informs a processor designation signal to a hardware simulator 2 at every delivery of the data, and sends delivered sorted data to the hardware simulator 2 comprehensively. |
申请公布号 |
JPH02115964(A) |
申请公布日期 |
1990.04.27 |
申请号 |
JP19880269805 |
申请日期 |
1988.10.25 |
申请人 |
NEC CORP;HOKURIKU NIPPON DENKI SOFTWARE KK |
发明人 |
ISHIKURA HIROSHI;NAKADA MASARU |
分类号 |
G06F17/50;G06F11/26;G06F15/16;G06F19/00 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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