| 摘要 |
<p>PURPOSE:To eliminate the need for two opposite clock signals by avoiding a data transmission gate transmitting a signal from a master section to a slave section from being turned on even if there is a period when a clock signal and its inverting signal go both to an H or an L level. CONSTITUTION:When a clock signal (CL)phi and its inverted signal, the inverse of phi are both at an H level, although a gate 5 and a transistor(TR) 8a are turned on but a TR 8b is turned off, data of a master section 3 is not transferred to a slave section 4. When the clock CLphi goes to an L level and the inverse of phi goes to an H level, the TRs 8a, 8b are both turned on and data of the master section 3 is transferred to the slave section 4. When the clock CLphi and the inverse of phi go both to an L level, the TR 8a is turned off and the data of the master section 3 is not transferred to the slave section 4.</p> |
