| 发明名称 |
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| 摘要 |
A treble-control circuit which exhibits a particularly low noise level and which can be controlled digitally in a simple manner. The treble control circuit comprises an amplifier having an output connected to the arrangement of a capacitor in series with a resistor chain. The tappings of said resistor chain are connected to an inverting input of the amplifier via a first switch and to the output of the treble control circuit via a second switch. |
| 申请公布号 |
JPH0214805(B2) |
申请公布日期 |
1990.04.10 |
| 申请号 |
JP19810158267 |
申请日期 |
1981.10.06 |
| 申请人 |
FUIRITSUPUSU FURUUIRANPENFUABURIKEN NV |
发明人 |
ERUNSUTOOAUGUSUTO KIRIAN;BIRUHERUMU GURATSUFUENBERUGERU;AIZE KARERU DEIYUKUMANSU;RUDEI YOHAN FUAN DERU PURATSUSHE |
| 分类号 |
H04B1/62;H03G3/00;H03G3/12;H03G5/00;H03G5/02;H03G5/04 |
主分类号 |
H04B1/62 |
| 代理机构 |
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