发明名称 ROM OF MASTER SLICE SYSTEM INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To enable rational arrangement and wiring by a method wherein a plurality of microcells having selector function constituted only of transmission gates and inverters are used, and an ROM of arbitrary capacity is constituted by combining said microcells. CONSTITUTION:A selector selecting one output from 2<n> inputs is constituted of a circuit 301 of analog switches and a circuit 302 controlling the analog switches. Three inputs AD0, AD1, AD2 are provided for address selection. By controlling them, one of input terminals D10, D11,...,D17 and D20, D21,...,D27 can be selected for the outputs D1, D2 of an ROM. Thereby, in a master slice system LSI, an arbitrary number of ROM's of arbitrary capacity can be used without decreasing the working efficiency of basic cells arranged on a chip.
申请公布号 JPH0286168(A) 申请公布日期 1990.03.27
申请号 JP19880237565 申请日期 1988.09.22
申请人 SEIKO EPSON CORP 发明人 MIZUNO MASAO
分类号 H01L21/822;G11C11/401;H01L21/82;H01L27/04;H01L27/10;H01L27/118 主分类号 H01L21/822
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