发明名称 Programmable logic device with array blocks with programmable clocking
摘要 A programmable logic device having a relatively small number of programmable product terms ("P-terms") feeding each fixed combinatorial logic device, and additional "expander" programmable P-terms which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitably programming the P-terms feeding the fixed devices. More complex logic functions can be performed by suitably programming the required number of expander P-terms, and then combining the outputs of those P-terms by means of another P-term. In addition, a programmable interconnect array is provided to allow certain inputs to the device to be applied to any programmable portion of the device, and also to allow the outputs of at least one of the fixed devices to be also applied to any programmable portion of the device.
申请公布号 US4912342(A) 申请公布日期 1990.03.27
申请号 US19890407411 申请日期 1989.09.14
申请人 发明人
分类号 H03K19/177 主分类号 H03K19/177
代理机构 代理人
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