| 摘要 |
PURPOSE:To realize high speed advancement of operation speed of a semiconductor integrated circuit device having DRAM by making wiring layers at the first and second layers into the wiring layers for signal transmission which are connected electrically at every specified interval. CONSTITUTION:In DRAM1, standard clock signal generating circuits (RAS and/or CAS) which are arranged respectively on opposite short sides of a rectangular chip and address circuits (XAB, YAB) are provided extendedly along the long side of the rectangular chip and are connected with standard clock signal wires in short-circuited two-layer wiring structure. Hereby, the resistance value of the standard clock signal wiring is reduced as compared with the case of single layer wiring structure, and high speed advancement of the transmission speed of standard clock signals is achieved. Hereby, the margin of address set-up time and address hold time improves, and high speed advancement of the operation speed of the DRAM1 can be achieved. |
