| 摘要 |
PURPOSE:To minimize the size of a semiconductor device for making a large scale integrated circuit by a method wherein adjacent two regions are exposed using the same alignment marks to reduce the margin with the alignment slip of a junction part. CONSTITUTION:First, during the pre-wiring process such as element isolating process, etc., a stepped part is previously formed between an alignment mark 1 and another alignment mark 2. Secondly, during the later wiring process, the surface is coated with a wiring metal and after further coating with a positive type photoresist, an exposure region 3 is aligned using the marks 1 and 2 to perform the exposure. Another exposure region 4 is exposed using the same marks 1 and 2 as well as another mask different from that for the region 3. The whole body is developed to form a wiring pattern of the resist. Later, the resist is released by metallic etching process to form a specified wiring. Through these procedures, the size of a semiconductor device is minimized to make a large scale integrated circuit (LSI). |
