发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT OF GATE ARRAY SYSTEM
摘要 PURPOSE:To restrain the increase of power consumption caused by a delay circuit and the decrease of yield by providing a basic cell in which the gate electrode of an MOS transistor for constituting a delay gate concurrently serves as a contact part with the wiring of a gate electrode of an MOS transistor for constituting a logic gate. CONSTITUTION:A P-channel MOS transistor region 3 for constituting a delay gate and an N-channel MOS transistor region 4 for constituting a delay gate are formed, in the manner in which a polysilicon gate electrode 5 of transistor regions 1, 2 for constituting logic gates is used in common. In a contact region 6, a polysilicon film, which is thickened in order to be in contact with metal wiring arranged at a contact part with metal wiring formed by thickening the polysilicon film, is used as the gate electrode of a transistor for a delay circuit.
申请公布号 JPH0246767(A) 申请公布日期 1990.02.16
申请号 JP19880198309 申请日期 1988.08.08
申请人 NEC CORP 发明人 MATSUDA YUKIHIKO
分类号 H01L21/82;H01L27/118;H03K19/173 主分类号 H01L21/82
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