| 摘要 |
<p>PURPOSE:To decrease the skew of a clock signal between respective memory elements by partitioning each memory element into small blocks, providing a buffer circuit for each small block, and decreasing the number of the steps of a clock driver. CONSTITUTION:Each small block 2 is formed at every memory elements 5a and 5b, which are either adjacent to each other in a physical layout or having high logical degree of coupling, and a clock signal phi generated in a clock signal generating part 1 is inverted and supplied to the small block 2. Further, the input of the clock signal phi is inhibited by a control signal 7, and since the interval between two different small blocks 2 is also the small block 2, which is never controlled by the control signal 7, and the clock signal phi can be obtained in the small block 2 to limit the input of the clock signal phi with one step of an inverting buffer circuit 4 and the control signal 7 only through a transmission gate 8 and two steps of the inverting buffer circuit 4, the delay between the clock signal phi controlled by the control signal 7 and the clock signal phi which is never controlled by the control signal 7 can be suppressed to the delay for one step of the gate, and the skew of the input of the clock signal phi to the memory elements 5a and 5b can be minimized.</p> |
