| 摘要 |
PURPOSE: To enable the formation of drain-to-gate spacing and gate-to-source spacing which are defined in a self-aligned mode by using a particular gate process in the manufacture of a gallium arsenide field effect transistor. CONSTITUTION: Following the formation of a lightly doped N-channel area 37, an insulating layer 38 is doposited on the surface 39 of a wafer 36, and a photoresist material layer 40 is provided on the surface of the insulating layer 38. Then, a source implantation region 41, a gate opening 42, a drain implantation region 43 are defined by using a mask. Then, a photoresist 40 is patterned according to a photolithographic process and the photoresist is removed. Therefore, the distance between the drain implantation region opening 43 and the gate opening implantation region 42 can be made larger than the distance between the source injection area 41 and the gate opening 42 so that an effective electric characteristic can be obtained. Thus, isolation of a drain region 46 from the end part adjacent to a gate 49 can be manufactured in a mode fixed by the mask.
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