发明名称 PHASE LOCKED OSCILLATOR
摘要 PURPOSE:To compensate an output offset of a sampling phase comparator and to hold synchronization stably by varying a bias voltage of the sampling phase comparator in following to a change in the bias voltage of a loop filter. CONSTITUTION:Assuming an offset voltage caused by a sampling phase comparator 1 as V0, a 1st bias voltage 6 as V1, and a 2nd bias voltage 7 as V2. At first, in the absence of temperature or power fluctuation, the 1st bias voltage 6 V1 is adjusted so as to compensate a voltage V0+V2 being the sum of the offset voltage V0 and the 2nd bias voltage V2 caused in the phase comparator 1. Then in the presence of a voltage fluctuation, since the resistance of resistors 11, 12, 13, 14 is sufficiently larger than that of resistors 9, 10, the 2nd bias voltage V2 varies with the 1st bias voltage 6 V1 and the bias voltage V0+V2 of the bias phase comparator 1 compensated by the voltage V1 is compensated because it follows the bias voltage of the loop filter 4.
申请公布号 JPH0225111(A) 申请公布日期 1990.01.26
申请号 JP19880173655 申请日期 1988.07.14
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YAMAKAWA KUNIO
分类号 H03L7/093;H03L7/08 主分类号 H03L7/093
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