Memory device containing a static RAM memory that is adapted for executing a self-test, and integrated circuit containing such a device as an embedded static RAM memory.

摘要

There is described a memory device that contains a static RAM-memory. This is provided with data input and date output registers, an address register, and a control register for storing various control signals. The RAM has three principal modes: a. in a normal mode, all registers are accessible externally so that the memory may fulfill its standard function, b. in a scan-state, all the cited register constitute a synchronous shift register that may be serially written with a test pattern and serially read with a result pattern; in this way the memory may be subjected to a test according to the scan test principle, c. in a self test state the communication with the outer world is shut off, the address register counts through successive addresses, the memory is cycled through read-modify or read-modify-read operations, and the data read is conversed to a signature pattern for subsequent scan-out. In this way a quasi stand-alone test facility is realized. Various additonal features may be implemented.