发明名称 CLOCK HOLD OVER CIRCUIT
摘要 PURPOSE: To maintain the accuracy of a clock hold-over circuit and to make it possible to supply also a switching clock signal by the combiniation of a digital circuit and a local frequency source by preparing a part depending upon time and temperature and selecting the parameter of the part within a required allowable range. CONSTITUTION: A countable signal is supplied from a monitor 26 to a counter 45 through a line 43, and when the signal is an input reference clock signal 10, a compensation value valid for a local clock reference signal 36 is generated from the counter 45. When the signal 10 disappears or becomes an invalid value, a parallel load enable signal is supplied from the monitor 26 to the counter 45 through a line 44 and a value finally stored in a register 46 is supplied to the counter 45. The value is supplied to a frequency synthesizer 38 through a line 48, an output from the synthesizer 38 is applied to the output of a mixer 35 and a phase comparator 34 through a circuit point, an output 33 from the comparator 34 is supplied to a VCO 29 through a switch 30, and the phase of the output 33 is synchronized with that of the reference signal 36 in the VCO 29.
申请公布号 JPH022722(A) 申请公布日期 1990.01.08
申请号 JP19880311821 申请日期 1988.12.09
申请人 SILICON GENERAL INC 发明人 TONII UOOREN;SUTEIIBUN JIYONSON
分类号 H03L7/14;H04L7/00;H04L7/033 主分类号 H03L7/14
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