| 摘要 |
PURPOSE:To improve the operating efficiency of a processor, by writing a specific code at each form in size, and interrupting the processor with the code. CONSTITUTION:When the specific code is read from an internal memory 102 on a data bus line 103B with direct memory access DMA, this data is inputted to a comparison circuit 105. Further, the specific code is latched in a latch circuit 106 in advance and when the specific code is read on the line 103B, a data is inputted to the circuit 105 from the circuit 106. Both the inputs are compared 105 and when they are coincident, a signal 105A is outputted to an NAND gate circuit 107. A signal 108A representing the designated range of the memory 102 is outputted from an address decoder 108. When the gate conditions with the signals 108A, 105A and a processor control signal 107A is established, a signal 107B is outputted from the circuit 107. This signal interrupts peripheral interruption control circuit of the processor 101. |
