| 摘要 |
PURPOSE:To facilitate the phase adjustment and to prevent a code error rate (B.E.R) from being deteriorated remarkably from the theoretical value even if the reception level is decreased by adopting the system such that a phase adjusting circuit adjusting the phase of a recovered clock signal extracted by a clock recovery circuit is processed digitally. CONSTITUTION:A reception signal from an input terminal 1 is shaped into a high level and a Low level by a waveform shaping circuit 2 and the result is inputted to a clock recovery circuit 3. Then the clock of 8Xfcl being 8 times the clock frequency fcl required is recovered in the circuit 3. Then the clock is given to a clock input terminal 9 of 1 shift register 6 in an 8Xfcl phase adjustment circuit 5 and the frequency of 8Xfcl is given to a frequency divider circuit 4, where the clock is subject to 1/8 frequency division, the result is inputted to an input terminal 10 of the shift register 6, the clock fcl is shifted by one bit each for n-bit by using the 8Xfcl clock, the result is inputted to a selector 7, which is controlled from the input terminals 9, 10, 11 and either of clocks e to l is outputted to the output terminal 12 of the selector 7. The frequency fcl of the recovered clock is given to a sampling circuit 8 to take the synchronization of the reception signal and the result is outputted at the output terminal 12. |
