发明名称 SEMICONDUCTOR DEVICE
摘要 PURPOSE:To constitute an enhancement type FET readily, by providing an embedded layer in an ordinary depression type FET buffer layer, and imparting a voltage. CONSTITUTION:A numeral 4 is the P type embedded layer provided in a semiinsulating GaAs substrate 1. A numeral 8 is an electrode, which applies a voltage to said embedded layer. A numeral 9 is a source electrode. A numeral 10 is a gate electrode. A numeral 11 is a drain electrode. The thickness of the buffer layer of the enhancement type FET can be the same as that when the ordinary depression type FET is formed. The control of the thickness need not be carried out as the case of the formation of the conventional enhancement type FET wherein precise control is required. The voltage is imparted to the electrode 8 so that a depletion layer is expanded to the buffer layer 2 from the P type embedded layer 4 in the buffer layer 2 beneath the gate of the FET as shown by dotted lines in the Figure, by the enhancement type FET. As a result, the gate electrode 10 is connected to the depletion layer which is expanded to the buffer layer 2, the source and the drain are separated, and the enhancement type FET can be operated.
申请公布号 JPS58148466(A) 申请公布日期 1983.09.03
申请号 JP19820032013 申请日期 1982.02.26
申请人 MITSUBISHI DENKI KK 发明人 UEDA MASAHIRO
分类号 H01L21/338;H01L27/095;H01L29/80;H01L29/812 主分类号 H01L21/338
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