发明名称 POWER-ON RESETTING SYSTEM
摘要 <p>PURPOSE:To prevent the cycle disturbance occurring among devices by continuing a reset state until a reference clock is stably supplied to release this reset state after the stable supply is secured with said reference clock and at the same time restarting the resetting action after a fixed time to initialize the phase of an internal clock of each device. CONSTITUTION:A period of time during which a reference clock 2 received from an external oscillator 11 is stabilized is decided by an RC time constant circuit. Then a first reset signal 7 is transmitted to each device via an OR circuit 16 in a period A during which a signal 1 is stabilized by a waveform shaping circuit 14. When the clock 2 is stabilized, the clocks of the oscillator 11 are counted by a counter 13 via an FF 12. Then an ON signal B is transmitted via the OR secured between signals 4 and 5 when the count value of the counter 13 reaches a prescribed level. The counter 13 transmits again a resetting signal 4 after the output of the signal B and the count value of the counter 13 is equal to a fixed level. Then the counter 13 applies the second resetting action to each device via the OR secured between both signals 4 and 5.</p>
申请公布号 JPH01284914(A) 申请公布日期 1989.11.16
申请号 JP19880115514 申请日期 1988.05.12
申请人 FUJITSU LTD 发明人 KITAHARA TAKESHI
分类号 G06F1/24;G06F1/00;G06F1/04 主分类号 G06F1/24
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