| 摘要 |
<p>PURPOSE:To match the rise phases with each other between a reference clock and its divided clock by using a D flip-flop which fetches the outputs of the 1/1 and 1/n dividers and a D latch. CONSTITUTION:A 1/2-reference clock divider 2 is prepared together with a 1/n divider 24 connected to the output of the divider 2, the D flip-flops 7-9 which latch the outputs of both dividers 2 and 24 via the reference clock, and a D latch 11 which is controlled so that the input/output is through with the reference clock used as an input. The outputs obtained by dividing the reference clock are received again by the flip-flops 7-9 and outputted by the reference clock. The reference clock itself passes through the latch 11 and is transmitted via a set/reset flip-flop 10. Thus the output of another divided clock can be matched with the delay time of the D flip-flop and to ensure the stable phase delay relation among clocks even with the LSI production method of a gate array, etc.</p> |
