发明名称 |
A LATCH CIRCUIT |
摘要 |
A latch circuit inputting and holding a write data including a data input terminal for receiving a write data signal and a feedback input terminal for receiving a feedback signal from an output terminal, the latch circuit through a feedback loop, wherein the output terminal of the latch circuit outputs the write data signal at a suitable timing. The latch circuit is operated such that a potential difference between a peak voltage of a logic amplitude and a reference voltage at the side at which the feedback signal is applied is set larger than a potential difference between the peak voltage of the logic amplitude and the reference voltage at the side at which the write data signal is applied. |
申请公布号 |
DE3573049(D1) |
申请公布日期 |
1989.10.19 |
申请号 |
DE19853573049 |
申请日期 |
1985.02.13 |
申请人 |
FUJITSU LIMITED |
发明人 |
SUZUKI, HIROKAZU;AKIYAMA, TAKEHIRO;MORITA, TERUO |
分类号 |
H03K3/286;H03K3/013;H03K3/0233;H03K3/2885;(IPC1-7):H03K3/288 |
主分类号 |
H03K3/286 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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