| 摘要 |
PURPOSE:To quicken the response of a PLL and to improve its stability by not limiting a change point when the response of the PLL is quickened and limiting one change point when the stability is improved. CONSTITUTION:A synchronizing detection circuit 5 compares an edge signal outputted from an edge detection circuit 2 with a retiming clock signal outputted from a PLL circuit 7 and outputs a limit selection signal when the phases are close to each other and outputs a full selection signal when the phases are parted. The PLL circuit 7 applies a well known phase synchronization based on a trigger signal outputted from the gate circuit 4 to receiver the retiming clock. Thus, in the base of quickening the response of the PLL, both change points are given to the PLL and in the case of improving the stability, one change point is fed to the PLL among change points from a space signals to a positive mark signal or to a negative mark signal and changing between the positive and negative mark signals. |
