| 摘要 |
PURPOSE:To eliminate the need for plural input/output controllers and peripheral equipments by providing a DMA transfer circuit having FIFO structure for performing DMA transfer at a high speed and a data generating circuit which generates data to be DMA-transferred at the high speed when a high traffic test of a bus is conducted. CONSTITUTION:A main control circuit 7 sends a DMA transfer start signal 101 to a DMA transfer control circuit 12 to start the DMA transfer and the DMA transfer control circuit 12 inputs the data from a main storage device 2 through the bus 3 and a bus interface circuit 4 and outputs the data to an FIFO 8. The main control circuit 7 when detecting the data being inputted to the FIFO 8 with an FIFO control signal 106 does not use the input data and performs data input operation from the FIFO 8 repeatedly during the DMA transfer. Thus, a state wherein the data to be DMA-transferred is inputted to the FIFO 8 is generated at all times, so the DMA transfer which is performed fast at the time of the high traffic test is enabled and even when no peripheral equipment is connected, the high traffic test is conducted. |
