Self-initializing 1,7 code decoder with low sensitivity to errors in preamble

摘要

A 1,7 decoder is repeatedly initialized during reading of the synchrofield of the record. The decoder includes an oscillator responsive to the record to produce a binary read signal having a frequency f. A first divider produces a source data clock signal having a frequency 2/3 f. A second divider produces a data partition clock signal having a frequency 1/3 f. A phase synchronizer is responsive to the data partition clock signal to synchronize the source data clock signal. An initializer is responsive to the read signal recovered from the preamble of the record to synchronize the data partition clock signal.